Applying Power Gating on D Flip-Flops

• Authors
• Authors and affiliations
• More About Author(s)

---

Statstics

Abstract:

This paper’s purpose is to document and analyze the effectiveness of power gating when applied to D flip-flops. We will use a master-slave transmission gate logic architecture to build a D flip-flop that has minimum power leakage. Simulations will be executed on: D flip-flop without power gating, D flip-flop with a header power gating, footed power gating, and stacked power gating. After that we will analyze and note the improvement that the power gating has on the D flip-flop when it comes to its power leakage. The simulation will be done using Cadence PSpice A/D Lite program using transistors of 32 nm technology transistors. The simulation will reveal when power is gating worth the implementation, since adding extra transistors by itself affects the active power consumption negatively.

Keywords:

Power gating, activity factor, D flip-flop, Leakage power.