Software Defined Radio (SDR) has the flexibility to modify the characteristics of the receiving and transmitting radio device, without physically adjusting the hardware, due to development in the system. Because of the increasing need for wireless communication applications so as to enable consumers to communicate anywhere through information led to the emergence of many communication devices to include the large amount of applications that every one of the devices needs power and thereby increase the total power. This study confirms that the wireless communication system for secured transmit data, fast and inexpensive; can be done by implementing using Partial Reconfiguration (PR) modern technology in FPGA developing based on SDR. The Speed and performance can be improved. The area also can be decreased. The new Xilinx, Vertex Series FPGA, provides the provision of PR. The power consumption can be reduced by applying power reduction techniques in the blocks. The combination of MATLAB (Simulink and M-file) and Simulink HDL Coder offers flexible capabilities for analysis, design; simulation, implementation, and verification. With all these capabilities, in a single system to reduce the time spent tuning for reducing the algorithms and models during rapid prototyping and experimentation and less time on HDL coding.
This study contributes in the existing literature review for implementing MC-CDMA wireless communication system using Partial Reconfiguration (PR) that is a new technology in FPGA.
G. F. Kasperski, O. Pierrelee, F. Dotto, and M. Sarlotte, "High data rate fully flexible sdr modem advanced configurable architecture & development methodology," presented at the IEEE Design, Automation & Test in Europe Conference & Exhibition, 2009.
A. Kumar, Y. I. Liu, and D. J. Sengupta, "Evolution of mobile wireless communication networks: 1G to 4G," International Journal of Electronics & Communication Technology, vol. 1, pp. 68-72, 2010. View at Google Scholar
M. Junaid, A. Farooq, and A. Shah, "Evolution and development towards 4th generation (4G) mobile communication systems," Journal of American Science, vol. 6, pp. 63-68, 2010. View at Google Scholar
R. Khan, A. H. M. Islam, and M. Rakibuddin, "Evolution of CDMA one and development of CDMA 2000 convergence and harmonization," Asian Journal of Information Technology, vol. 4, pp. 935-939, 2005. View at Google Scholar
B. Woerner and M. Howlader, "Research directions for fourth generation wireless," presented at the Tenth IEEE International Workshops, 2001.
S. Kaur and G. Bharti, "Orthogonal frequency division multiplexer in wireless communication systems, a review," International Journal of Advanced Research in Computer Engineering & Technology, vol. 1, p. 125, 2012. View at Google Scholar
S. Amir and M. Asif, "Analytical study of MC-CDMA-TCM over multi-path rayleigh," presented at the International Conference on Computer Engineering and Applications, 2011.
M. Dillinger, K. Madani, and N. Alonistioti, Software defined radio: Architectures systems and functions. England: John Wiley & Sons Ltd, 2003.
A. Karmakar and A. Sinha, "A novel architecture of a reconfigurable radio processor for implementing different modulation schemes," presented at the IEEE Computer Research and Development (ICCRD) 3rd International Conference, 2011.
R. Raut and K. Kulat, "SDR design for cognitive radio," presented at the Fourth International Conference on Modeling Simulation and Applied Optimization, IEEE, 2011.
Simulink, Simulink HDL coder: The Math-Work Inc, 2011.
V. A. Pedroni, Circuit design with VHDL. Massachusetts Institute of Technology Press, 2004.
H. Hassan, H. C. Ku, K. Y. Che, and N. I. S. Bakhtir, "Low complexity SDR transceiver design using simulink, Matlab, and Xilinx," presented at the ICT Convergence (ICTC), International Conference, IEEE, 2012.
Xilinx, "Xilinx Plan Ahead Software Tutorial Overview of the Partial Reconfiguration Flow, UG743 (v14.1)," 2012.
R. N. Pittman, "Partial reconfiguration: A simple tutorial," Technical Report, MSR-TR 2012-19, Microsoft Research2012a.
D. Dye, "Partial reconfiguration of Xilinx FPGAs using ISE design suite," Xilinx, 2011.
P. Leppanen, J. Reinil, and A. Nykanen, "Software radio - an alternative for the future in wireless personal and multimedia communications," presented at the IEEE Personal Wireless Communication International Conference, 1999.
D. Murotake, J. Oates, and A. Fuchs, "Real-time implementation of a reconfigurable IMT-2000 base station channel modem," IEEE Communications Magazine, vol. 38, pp. 148-152, 2000. View at Google Scholar | View at Publisher
Y. Sun, A. Nix, D. Milford, and D. Bull, "Low complexity synchronization, equalization and diversity combining for home-based hiperlan /l transceivers," in IEEE Vehicular Technology Conference Proceedings, 2000, pp. 2242-2246.
X. Reves, A. Gelonch, and F. Casadevall, "Software radio implementation of a DS-CDMA indoor subsystem based on FPGA devices," Personal, Indoor and Mobile Radio Communications, IEEE, vol. 1, pp. D-86-D-90, 2001.
B. G. Kang, "Design, and implementations of a software defined radio scheme based modem for high-speed multimedia data service," presented at the IEEE Proceedings Tencon’02 Conference, 2002.
F. C. Tormo and J. V. Coquillat, "Optimized FPGA implementation of quadrature DDS," presented at the IEEE International Symposium, 2002.
Y. D. Chuang, Y. S. Chang, and R. H. Wu, "SDRsim: A PC-based simulator of software defined radio," presented at the IEEE Telecommunications 10th International Conference, 2003.
V. N. Doan and T. Le-Ngoc, "Low complexity optimal symmetric interpolation filters for SDR receiver," presented at the IEEE Canadian Conference, 2003.
A. Blaickner, S. Albl, and W. Scherr, "Configurable computing architectures for wireless and software defined radio - A FPGA prototyping experience using high-level design-tool-chains," presented at the IEEE International Symposium, 2004.
P. M. Mannan, "Framework for the design and implementation of software defined radio based wireless communication system," M.Sc. Thesis, University of Akron, 2005.
P. Isomaki and N. Avessta, "Rapid refinable SoC SDR design," presented at the IEEE International Symposium, 2005.
P. J. Green and D. P. Taylor, "Implementation of four real-time software defined receivers and a space-time decoder using Xilinx virtex 2 Pro field programmable gate array," presented at the Third IEEE International Workshop on Electronic Design, 2005.
L. Chaari, M. Fourati, N. Masmoudi, and L. Kamoun, "Re-configurability study for digital baseband processing unit for multimode handset architectures," presented at the IEEE Wireless Conference, 2006.
E. O. Garcia, R. Cumplido, and M. Arias, "Pipelined CORDIC design on FPGA for a digital sine and cosine waves generator," presented at the IEEE 3rd International Conference, 2006.
A. P. Vinod, E. M. K. Lai, and S. Emmanuel, "Implementation of low-power and high-speed higher order channel filters for software radio receivers," presented at the IEEE International Symposium, 2006.
G. J. Minden, J. B. Evans, and L. Searl, "KUAR: A flexible software-defined radio development platform," presented at the IEEE International Symposium, 2007.
Y. Tachwali and H. Refai, "Implementation of a BPSK transceiver on hybrid software defined radio platforms," presented at the IEEE 3rd International Conference, 2008.
G. Elamary, G. Chester, and J. Neasham, "A simple digital VHDL QPSK modulator designed using CPLD/FPGAs for biomedical devices applications," in Proceedings of the World Congress on Engineering London U.K, 2009.
A. Y. Jaber, L. A. Latiff, A. Norulhusna, A. N. Abdalla, and A. K. Nahar, "Peak-to-average power ratio method to improve the performance of multicarrier model system," Publish Research Journal of Applied Sciences, Engineering and Technology, vol. 10, 2015.
J. Gurugubelli and I. Chakrabarti, "Design and implementation of a generalized parametrizable modulator for a reconfigurable radio," presented at the IEEE Conference Publications, 2010.
W. Changrui, K. Chao, X. Shigen, and C. Huizhi, "Design and FPGA implementation of flexible and efficiency digital down converter," presented at the IEEE 10th International Conference, 2010.
A. S. Rodriguez, M. C. Mensinger, I. S. Ahn, and Y. Lu, "Model-based software-defined radio (SDR) design using FPGA," presented at the IEEE International Conference, 2011.
S. O. Popsscu and A. S. Gontena, "Performance comparison of the BPSK and QPSK modulation techniques on FPGA," presented at the IEEE 17th International Symposium for Design and Technology in Electronic Packaging, 2011.
A. Tabassam, F. Ali, S. Kalsait, and M. Suleman, "Building software- defined radios in MATLAB simulink – a step towards cognitive radios," presented at the IEEE, UKSim 13th International Conference on Modelling and Simulation, 2011.
R. D. Raut and K. D. Kulat, "SDR design for cognitive radio," presented at the 4th International Conference on Modelling, Simulation and Applied Optimization (ICMSAO), IEEE, 2011.
S. Bhattacharjee, S. Sil, S. Dey, and A. Chakrabarti, "Simulation, design and analysis of a low power MIMO-OFDM system and its implementation on FPGA," presented at the International Conference on Recent Trends in Information Systems, IEEE, 2011.
R. Supriya, L. S. Murugan, and R. C. Biradar, "Design and implementation of software defined radio using Xilinx system generator," 2012.
M. Donelli and C. Sacchi, "Implementation of a low-cost reconfigurable antenna array for SDR-based communication systems," presented at the Aerospace Conference, IEEE, 2012.
S. Usman, A. Mahmood, and M. R. Ashraf, "Porting of OSSIE on texas instrument’s DAVINCI SoC based SDR platform," presented at the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discover, IEEE, 2012.
T. Kazaz, M. Kulin, and M. Hadzialic, "Design and implementation of SDR based QPSK modulator on FPGA," presented at the Information & Communication Technology Electronics & Microelectronics (MIPRO), 36th International Convention on IEEE Conference Publications, Opatija, Croatia, 2013.
M. B. Sruthi, M. Abirami, A. Manikkoth, R. Gandhiraj, and K. P. Soman, "Low-cost digital transceiver design for software defined radio using RTL-SDR," presented at the International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), IEEE, 2013.
Y. G. Jeong, J. S. Kim, and M. J. Kim, "Implementation of code tracking loop for PC'S system," in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, 1996, pp. 49-52.
P. Shamain and L. B. Milstein, "Minimum mean square error (MMSE) receiver employing 16-QAM in CDMA channel with narrowband Gaussian interference," in Military Communications Conference Proceedings, IEEE, 1999, pp. 826-830.
P. Jain and R. Buehrer, "Implementation of adaptive modulation on the sunrise software radio," Circuits and Systems, IEEE, vol. 3, pp. 405-408, 2002. View at Google Scholar
K. E. M. Osman, "Design of direct sequence code division multiple access (DS-CDMA) wireless transmitter using field programmable gate array," Putra Malaysia University, M.Sc., Thesis, 2002.
H. Park, Y. Park, and C. Kim, "A design of QAM modulator for multicode WCDMA," presented at the Radio and Wireless Conference, IEEE, 2003.
L. K. Cheng, "Design of OFDM transmitter and receiver using FPGA," Malaysia University of Technology, M.Sc. Thesis, 2004.
H. N. Al-Shamary, "Design and implementation of direct sequence spread spectrum system using field programmable gate array," University of Technology, Ph.D. Thesis, Department of Electrical Engineering, 2004.
G. Carcia and R. Cumplido, "On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004," presented at the International Conference on Reconfigurable Computing and FPGAs, IEEE, 2005.
B. Xia and J. Wang, "Analytical study of QAM with interference cancellation for high-speed multicode CDMA," IEEE Transactions on Vehicular Technology, IEE/IEEE, vol. 54, pp. 1070-1080, 2005. View at Google Scholar | View at Publisher
R. Annarajjala, "Comments on exact error rate analysis of diversity 16-QAM with channel-estimation error," IEEE Transaction on Communication, IEE/IEEE, vol. 54, pp. 393- 396, 2006. View at Google Scholar | View at Publisher
A. Kaur, "Linear feedback shift registers in wireless communication systems," M.Sc Thesis, Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, India, 2006.
J. Carcia, J. A. Michell, G. Ruiz, and A. M. Buron, "FPGA realization of split-radix FFT processor," in Proceeding of SPIE, 2007.
K. E. Mohamed, B. M. Ali, and S. S. Jamuar, "Implementation of CDMA transmitter for a multi-standard SDR base band platform," presented at the IEEE of Asia-Pacific Conference on Communications, 2007.
H. Alasady and M. Ibnkahla, "Design and hardware implementation of look-up table predistortion on ALTERA stratix DSP board," presented at the Canadian Conference on Electrical and Computer Engineering, IEEE, 2008.
L. A. Tuan and K. Araki, "A group of modulation schemes for adaptive modulation," presented at the Singapore International Conference on Communication Systems, IEEE, 2008.
F. M. Gutierrez, "Implementation of a Tx/Rx OFDM system in an FPGA," M. Sc. Thesis, Telecommunication Engineering & Management, University at Politecnica De Catalunya, 2009.
G. De Angelis, G. Baruffa, and S. Cacopardi, "Parallel PN code acquisition for wireless positioning in CDMA handsets," presented at the 5th Advanced Satellite Multimedia Systems Conference and the 11th Signal Processing for Space Communications Workshop, IEEE, 2010.
A. K. Nahar and Y. Rahayu, "Design of selectable modems for MC-CDMA based on software defined radio," International Journal of Engineering Technology and Sciences, vol. 3, pp. 1-7, 2015. View at Google Scholar
A. K. Nahar and Y. Rahayu, "Design and implementation of MC-CDMA wireless communication system using partial reconfiguration in FPGA—A review," International Journal of Advancements in Communication Technologies– IJACT, vol. 2, pp. 42-46, 2015.
M. A. Mohamed, A. S. Samarah, and M. I. FathAllah, "A novel implementation of OFDM using FPGA," International Journal of Computer Science and Network Security, pp. 43-48, 2011. View at Google Scholar
T. S. Mahbub, S. Ahmed, and I. R. Rokon, "Transmitter implementation using DS-CDMA technique in FPGA using verilog HDL," presented at the International Conference on Electrical, Electronics and Civil Engineering, 2011.
A. Amsavalli and K. R. Kashwan, "FPGA implementation of low complexity VLSI architecture for DS-CDMA communication system," International Journal of Computer Applications, vol. 42, pp. 27-34, 2012. View at Google Scholar | View at Publisher
V. Corvino, V. A. Carniani, and R. Verdone, "Cross-layer scheduling over a heterogeneous opportunistic emergency-deployed wireless network," International Journal of Pervasive Computing and Communications, vol. 5, pp. 312 – 331, 2009. View at Google Scholar | View at PublisherJ.
Delorme, J. Martin, A. Nafkha, C. Moy, F. Clermidy, P. Leray, and J. Palicot, "A FPGA partial reconfiguration design approach for cognitive radio based on NoC architecture," presented at the International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, Joint 6th, NEWCAS-TAISA, 2008.
R. Kumar, R. C. Joshi, and K. S. N. Raju, "A FPGA partial reconfiguration design approach for RASIP SDR," presented at the India Conference (INDICON), Annual IEEE, 2009.
P. S. Ostler, M. J. Wirthlin, and J. E. Jensen, "FPGA bootstrapping on PCIe using partial reconfiguration," presented at the International Conference on Reconfigurable Computing and FPGAs, IEEE, 2011.
M. Rozkovec, J. Jeníek, and O. Novák, "An evaluation of the application dependent FPGA test method," presented at the International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2012.
N. Joseph and K. P. Nirmal, "Power consumption reduction in an SDR based wireless communication system using partial reconfigurable FPGA," International Journal of VLSI Design & Communication Systems (VLSICS), vol. 3, 203-210 2012. View at Google Scholar | View at Publisher
M. Orlandic and K. Svarstad, "An area efficient hardware architecture design for H.264/AVC Intra prediction reconstruction path based on partial reconfiguration," presented at the Design and Diagnostics of Electronic Circuits & Systems (DDECS), 16th International Symposium, IEEE, 2013.
Y. I. Hori, T. Katashita, and K. Kobara, "Energy and area saving effect of dynamic partial reconfiguration on a 28-nm process FPGA," presented at the 2nd Global Conference on Consumer Electronics (GCCE), IEEE, 2013.
A. Kumar, "FPGA implementation of PSK modems using partial reconfiguration for SDR and CR applications," presented at the India Conference (INDICON) (s)Annual IEEE, 2012.
A. Kumar, "Low power implementation of PSK modems in FPGA with reconfigurable filter and digital NCO using PR for SDR and CR applications," presented at the Information & Communication Technologies (ICT) Conference on Digital Object Identifier: 10.1109/CICT.2013.6558215, IEEE, 2013.
A. Kumar, "FPGA implementation of QAM modems using PR for reconfigurable wireless radios," presented at the International Conference on Microelectronics, Communication and Renewable Energy (ICMiCR) IEEE, 2013.
A. Kumar, "A SoC based partially reconfigurable OFDM transmitters for cognitive radios," presented at the International Conference on Control Communication and Computing (ICCC) IEEE, 2013.
A. Kumar, "An implementation of DPD in FPGA with a soft processor using partial reconfiguration for wireless radios," presented at the Conference on Information and Communication Technologies (ICT 2013) IEEE, 2013.
A. Kumar, "A secure frequency hopping synthesizer for reconfigurable wireless radios," presented at the Conference on Information and Communication Technologies (ICT 2013), IEEE, 2013.
C. Vennila, K. Suresh, R. Rathor, G. Lakshminarayanan, and S. B. Ko, "Dynamic partial reconfigurable adaptive transceiver for ofdm based cognitive radio," presented at the Canadian Conference Of Electrical And Computer Engineering (CCECE), IEEE, 2013.
A. K. Nahar, Y. Rahayu, and A. Y. Jaber, "Design the MC-CDMA system with LS-PSO channel estimation based FPGA," Research Journal of Applied Sciences, Engineering, and Technology, vol. 10, pp. 1051-1061, 2015. View at Google Scholar | View at Publisher
N. P. Raut and A. V. Gokhale, "FPGA implementation for image processing algorithms using Xilinx system generator," IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), vol. 2, pp. 26-36, 2013. View at Google Scholar
R. N. Pittman, "Partial reconfiguration: A simple tutorial," Microsoft Research, Technical Report, a Tutorial for XILINX FPGAs, Version 1.02012b.
A. K. Nahar and Y. Rahayu, "VHDL implementation of RPS technique for PAPR reduction in MC-CDMA," NNGT International Journal of Networking and Communication, vol. 4, pp. 1-11, 2015.
A. K. Nahar and K. H. B. Gazali, "PAPR reduction based on proposed rotating phase shift technique in MC-CDMA using FPGA," International Journal of Communications, Network and System Sciences, vol. 8, pp. 249-259, 2015. View at Google Scholar | View at Publisher
This study received no specific financial support.
The authors declare that they have no competing interests.
All authors contributed equally to the conception and design of the study.